1. Field of the Invention
The present invention relates to a solid state image sensor, a method for driving a solid state image sensor, an imaging apparatus, and an electronic device.
2. Description of the Related Art
Amplified solid state image sensors are one category of solid state image sensors that use an X-Y addressing scheme. Amplified solid state image sensors include, for example, CMOS (Complementary Metal Oxide Semiconductor) solid state image sensors (this also includes MOS devices). Hereinafter, such solid state image sensors are referred to as CMOS image sensors.
In a CMOS image sensor, a plurality of pixels containing photodetectors are arranged in a two-dimensional array. In addition to a photodetector, each individual pixel also includes within its pixel boundary many component elements (transistors, for example) that constitute components such as a read gate, a reset gate, and an amplifier. For this reason, there exist limits when attempting to miniaturize pixels.
Recently, however, multi-pixel sharing architectures have been proposed, wherein a portion of the component elements that have been typically provided on a per-pixel basis are instead shared among a plurality of pixels. In so doing, the per-pixel footprint (excluding the photodetector) is suppressed. Such multi-pixel sharing architectures are becoming a vital technology in the design of miniaturized pixels for CMOS imagers.
One such multi-pixel function sharing architecture involves arranging, between two photodetectors, a charge-to-voltage converter supplying the two photodetectors, as well as other component element groups (i.e., transistor groups constituting a reset gate and other components) (see, for example, U.S. Pat. No. 6,423,994). Another architecture involves sharing a charge-to-voltage converter and other component element groups between two photodetectors, while additionally arranging the shared component element groups so as to be in-line with each photodetector (see, for example, Japanese Unexamined Patent Application Publication No. 2001-298177).
In such CMOS image sensors, the pixel architecture is typically front-illuminated such that incident light is captured on the front side, where the front side is taken to be the side upon which the metal layer with respect to the photodetectors is disposed. In contrast, however, there also exist back-illuminated pixel architectures such that incident light is captured on the back side, or in other words, the side opposite that of the metal layer (see, for example, Japanese Unexamined Patent Application Publication No. 2003-031785).
Meanwhile, in order to prevent charge overflowing from the photodetector from bleeding into an adjacent pixel, front-illuminated pixel architectures typically adopt the vertical overflow drain architecture shown in FIG. 1. This vertical overflow drain architecture involves setting the potential barrier of the floor of the photodetector (PD) 51 lower than the potential barrier under the transfer gate 53, and discarding charge overflowing from the photodetector 51 into the substrate 52.
Meanwhile, since there is no substrate in the back-illuminated pixel architecture, charge overflowing from the photodetectors is not discarded as described above. Thus, a back-illuminated pixel architecture adopts a horizontal overflow drain architecture, wherein charge overflowing from the photodetector 51 is passed under the transfer gate 53 and discarded into a floating diffusion (hereinafter referred to as an FD). Incidentally, preventing charge overflowing from the photodetector 51 from bleeding into an adjacent pixel also suppresses blooming (the phenomenon whereby portions not receiving incident light also appear bright).
Another anti-blooming technology involves activating an electronic anti-blooming shutter simultaneously with the electronic shutter that regulates the exposure time (i.e., the charge accumulation time). The electronic anti-blooming shutter is even activated with respect to pixel rows whose charge is not read at all during a single frame period (see, for example, Japanese Unexamined Patent Application Publication No. 2008-288904). This other anti-blooming technology is principally designed for front-illuminated solid state image sensors, and is configured to discard the charge of the photodetector 51 into the power supply via the FD 54.
In addition, in recent years apparatus that make use of solid state image sensors, such as digital still cameras and digital camcorders, are becoming more widely used. Moreover, in the field of mobile phones and similar mobile handsets, products incorporating camera functions are becoming the norm. There is a tendency for CMOS (Complementary Oxide Metal Semiconductor) image sensors (CIS) to be used rather than CCDs (Charge Coupled Devices) in such applications.
In a CIS, each pixel includes a photodetector (PD) as well as a transfer transistor (TRF). Typically, each pixel also includes a floating diffusion (FD), an amplifier transistor (AMP), a reset transistor (RST), and a selection transistor (SEL).
Although such CIS sensors are being applied to mobile phones, recently there has been demand for more detailed images. In order to meet this demand, pixel sizes have been miniaturized from 2.5 μm, to 2.0 μm, to 1.75 μm over the years, thereby realizing increased numbers of pixels. Meanwhile, there has also been demand for reduction in the size of the camera module, in order to make the mobile phone itself smaller in size. In order to meet this demand, the pixel size and the optics size has been reduced, thereby realizing a reduction in the size of the camera module. The demand for pixel size reduction is ongoing.
On the other hand, if the pixel size is made smaller, then the surface area of the photodiode that converts incident light into an electrical signal also becomes smaller. This results in a decrease in factors such as sensitivity and saturation signal strength, which degrades imaging performance. In order to prevent such degradation, it has been proposed that the floating diffusion, the amplifier transistor, the reset transistor, and the selection transistor be shared among a plurality of pixels. It has been proposed that by sharing, the number of transistors per pixel can be decreased, and the surface area of the photodiode can be increased.
For example, in the configuration proposed in Japanese Unexamined Patent Application Publication No. 2007-201863, the floating diffusion is shared among four pixels arranged in a 2×2 layout in the horizontal and vertical directions, and the surface area of the photodiode is increased. Furthermore, in the configuration proposed in Japanese Unexamined Patent Application Publication No. 2005-268537, the drain potential of the reset transistor and the drain potential of the amplifier transistor are set individually.
FIG. 25 illustrates an exemplary configuration of an imaging apparatus described in JP-A-2005-268537. The imaging apparatus shown in FIG. 25 is formed from two pixel units PD1 and PD2. The pixel unit PD1 includes: a photodiode 1 having photoelectric conversion functions; a transfer transistor 2 that transmits photocarriers accumulated in the photodiode 1 to a floating diffusion; and a reset transistor 3 for resetting the potential of the floating diffusion.
The pixel unit PD2 includes: a photodiode 4 having photoelectric conversion functions; a transfer transistor 5 that transmits photocarriers accumulated in the photodiode 4 to the floating diffusion; and an amplifier transistor 6 that amplifies and outputs the signal transmitted to the floating diffusion.
The pixel units PD1 and PD2 are electrically connected to each other by the floating diffusion. The photodiode 1 and the transfer transistor 2 are connected in series between a fixed potential GND and the floating diffusion. The gate of the transfer transistor 2 is electrically connected to a control terminal 7 that accepts a control signal TX1 as input. The reset transistor 3 is disposed between the floating diffusion FD and a control terminal 9, to which a control potential Vref1 is applied. The gate of the reset transistor 3 is electrically connected to a control terminal 8 that accepts a reset control signal RST as input.
The photodiode 4 and the transfer transistor 5 are connected in series between the fixed potential GND and the floating diffusion. The gate of the transfer transistor 5 is electrically connected to a control terminal 10 that accepts a control signal TX2 as input. The amplifier transistor 6 is disposed between a control terminal 11, to which a control potential Vref2 is applied, and an output terminal 12 that outputs the amplified signal. The gate of the amplifier transistor 6 is electrically connected to the floating diffusion FD.